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Driving Innovation in Automotive SoC Development
GROWING NEED FOR HIGH-PERFORMANCE IN-VEHICLE NETWORKS
The automotive industry has witnessed significant transformation in the past few years, triggered by various innovations such as Advanced Driver Assistance Systems (ADAS) and autonomous driving, as well as trends such as in-vehicle infotainment and mobile offices. All this has increased the semiconductor content in automobiles exponentially.
Earlier in-vehicle systems were architected with dedicated networks with differing protocols and different wires for different functions, which impacted data rates and performance. Given the huge volumes of data involved in ADAS, autonomous driving, infotainment systems and mobile office connectivity, the older standards no longer suffice and there is a shift towards consolidating the multiple networks and schemes into just a handful, with the objective of transferring a large volumes of data faster and minimizing response times. A related additional benefit is reducing vehicle weight to improve aerodynamics and performance.
DELIVERING NETLIST TO GDS IMPLEMENTATION FOR IN-VEHICLE-NETWORKS
SoC
The mixed-signal SoC was targeted for state-of-the-art connectivity and communications for the automotive market. Eteros Technologies Inc., our partner, was responsible for the Netlist to GDSII implementation for the SoC @7nm. We successfully taped-out two generations of the chip to date.
Solution Delivered
The scope of the engagement was implementation of Netlist to GDSII which included full-chip and partition-level PNR, STA sign-off, IR/EM analysis and sign-off, physical verification sign-off, DFT implementation (architecture, JTAG, Scan insertion, ATPG, simulations), AMS verification, characterization of AMS IPs, and AMS layout.
Tape-out Results
Eteros delivered on its promise of On time, first time right, every time meeting the client’s design specifications and schedule, and delivered multiple versions starting from test chip to production tape-outs.
On the first generation SoC, not only was Eteros responsible for the Netlist to GDS implementation, we were also an integral part of developing the flow. Additionally, we were tasked with developing an advanced AMS verification environment that allowed verification both in the digital and analog environments. Eteros developed VERILOG A models for this purpose. To allow for SoC timing sign-off using STA, we characterized complex analog blocks to generate .libs using industry standard library characterization tools.
At the SoC level, we delivered impressive results at sign off (both STA and DFM) on schedule. STA using Path Based Analysis was used to sign-off on timing. Automotive SoCs require strict adherence to quality and ISO standards during development. Eteros engineers are knowledgeable and well-versed in these requirements and use industry standard processes and methodologies developed by the customer to ensure compliance.
RIGHT-SIZED TEAM FOR ON-TIME, ON-COST DELIVERY
Eteros leveraged a combination of its in-house resources and its global talent pool with the precise expertise and skill sets required for the project. The engagement was executed with a right-sized lean
Eteros talented engineers includes specialist in the follow fields:
- Analog circuit design
- RTL design & architecture
- Design verification
- Design for test
- Backend / Layout
- Firmware/embedded software
Replay for more information!